In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. The term “FET” is used in the present application to denote a field effect transistor; the lower case ‘n’ and ‘p’ denote the conductivity of the transistor. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal plane.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have a high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×–4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobility on (110) Si is 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobility on (110) Si surfaces is significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Hybrid oriented substrates having planar surfaces with different crystallographic orientation have recently been developed. See, for example, U.S. patent application Ser. No. 10/250,241, filed Jun. 23, 2003. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. As discussed above, the electron mobility and hole mobility can be optimized independently by placing the nFET on a (100) surface and the pFET on a (110) surface.
In such technologies, the nFET is formed into a (100) SOI region of the hybrid substrate, while the pFET is formed into a (110) bulk-epi region. As is known to those skilled in the art, SOI devices generally have higher performance than bulk-like devices due to less parasitic capacitance. Hence, it is desirable to provide a semiconductor substrate that has separate SOI crystal orientations for both nFETs and pFETs.
In view of the above, there is a need to provide a hybrid substrate that has separate SOI regions with different crystal orientations.